In the fabrication of semiconductor integrated circuits (ICs), various structures and circuitry are typically formed on a semiconductor workpiece using a variety of techniques. For instance, various structures are formed, defined and/or electrically isolated from one another in the semiconductor workpiece utilizing various masking and etching processes. As feature sizes become smaller and smaller to accommodate increasing device densities, proper process control is of great importance.
One common technique utilized in defining structures is photolithography. In optical photolithography, for example, an optical mask is typically utilized to produce a pattern in a photoresist layer, wherein the photoresist layer overlies one or more other layers previously formed over a semiconductor substrate. The optical mask is positioned between the photoresist layer and a radiation source, and the photoresist layer is subjected to radiation, such as a visible light or ultraviolet radiation. Portions of the optical mask conventionally comprise a patterned opaque layer, (e.g., chromium), wherein the opaque layer prevents exposure of the underlying photoresist layer. Remaining portions of the optical mask, on the other hand, are transparent, thus allowing exposure of the underlying photoresist layer. Accordingly, an image of the optical mask is reproduced on the photoresist layer via the exposure of the photoresist layer to the radiation through the optical mask.
After exposure, a developer solution is typically introduced to the workpiece, wherein, depending on the type of photoresist material utilized (e.g., positive type or negative type), exposed photoresist material is either removed by the developer solution, or the exposed photoresist material becomes more resistant to dissolution by the developer solution. Thus, a patterned photoresist layer is accordingly formed over the one or more layers, wherein portions of the one or more layers are generally exposed. Material from the one or more layers is then selectively removed, such as by wet or dry etching, therein defining the desired various structures in the workpiece. Adequate control of both the photolithographic process, as well as the etch processes is thus important in achieving the desired resultant semiconductor device(s).
One problem experienced with conventional optical photolithography is a difficulty of obtaining uniform exposure of the photoresist layer underlying transparent portions of the mask. Generally, it is desirable that the light intensity exposing the photoresist be uniform to obtain optimum results. When substantially thick layers of photoresist material are used, the photoresist layer becomes partially transparent upon exposure, such that photoresist material at the surface of the underlying one or more layers is exposed a substantially similar extent as the photoresist at the outer surface. However, light that penetrates the photoresist is often reflected back toward the light source from the surface of the underlying one or more layers formed on the substrate. The angle at which the light is reflected is generally dependent on the topography of the surface of the underlying one or more layers and the type of material of the one or more layers. Further, the reflected light intensity can vary in the photoresist layer throughout its depth or partially though its depth, leading to non-uniform exposure and/or undesirable exposure of the photoresist material. Such exposure of the photoresist layer can lead to poorly controlled dimensions on features (e.g., gates, metal lines, etc.) of the IC.
In an attempt to minimize the variable reflection of light in a photoresist layer, antireflective coatings have been utilized. For example, an antireflective coating is formed over the one or more layers of the workpiece prior to the formation of the photoresist layer. Such antireflective coatings minimize photoresist exposure from surface reflections, and allow exposure across the photoresist layer to be controlled more easily from the radiation emitted from the radiation source incident on the photoresist material.
Antireflective coatings can comprise organic or inorganic materials. For example, inorganic materials, such as silicon-rich silicon dioxide, silicon-rich nitride, and silicon-rich oxynitride, have been utilized quite successfully as antireflective coatings, such as in the patterning of metal lines and polysilicon gates. FIGS. 1A-1C illustrate an exemplary semiconductor workpiece 10 during several stages of photolithographic processing. The workpiece 10 comprises a semiconductor substrate 12 having a gate oxide layer 14 and a polysilicon layer 16 formed thereon. As illustrated in FIG. 1A, a conventional inorganic antireflective coating (IARC) layer 18 has been formed over the polysilicon layer 16, and a photoresist layer 20 has been patterned over the IARC layer, using the advantageous antireflective properties of the IARC layer to more accurately define the patterned photoresist layer. The photoresist layer 20 thus defines exposed portions 22 of the IARC layer 18.
FIG. 1B illustrates the result of a conventional etch process, wherein the IARC layer 18, polysilicon layer 16, and gate oxide layer 14 is etched in the exposed portions 22 of FIG. 1A, and wherein the etch continues into the semiconductor substrate 12 by a first etch depth 24, typically on the order to 10-20 angstroms. The photoresist layer 20 is also shown as being removed in FIG. 1B, as the presence of the photoresist layer is no longer necessary or desired.
The IARC layer 18 is likewise unnecessary and undesirable for further processing. Accordingly, FIG. 1C illustrates the result of removing the IARC layer 18, wherein the IARC layer has been stripped or etched from the workpiece 10 by hot phosphoric acid. Conventionally, stripping of the IARC layer 18 is a relatively lengthy process, and during the hot phosphoric acid stripping of the IARC layer, the semiconductor substrate 12 is further removed to a second etch depth 26, typically on the order of 40-50 angstroms. As a result of the relatively long stripping of the IARC layer 18 in hot phosphoric acid, the relatively large second etch depth 26 can lead to transistor performance losses and other undesirable effects.
A well known electrical isolation technique is called trench isolation. In trench isolation, a trench is etched in the substrate and then filled with deposited oxide. Trench isolation is referred to as shallow trench isolation (STI) or deep trench isolation (DTI), depending on the depth of the trench etched in the substrate. FIGS. 2A-2C illustrate another workpiece 30 undergoing shallow trench isolation processing, wherein a pad oxide layer 32 is traditionally grown over a semiconductor substrate 34 and a nitride layer 36 is deposited over the pad oxide layer. A photoresist layer 38 illustrated in FIG. 2A is again utilized to pattern the nitride layer 36, the pad oxide layer 32, and the semiconductor substrate 34 (e.g., via an etch process), wherein the resultant structure is illustrated in FIG. 2B (the photoresist layer 38 has also been removed).
Subsequently, the nitride layer 36 is “pulled back” (e.g., via hot phosphoric acid) to reveal corners 40 of the semiconductor substrate 34 for subsequent oxidation treatment, as illustrated in FIG. 2C. The “pull back” of the nitride layer 36, however, further etches the semiconductor substrate 34, wherein active regions 42 of the semiconductor substrate are etched, therein causing critical dimension (CD) losses 44 in the active regions, wherein performance can be negatively impacted.